Pulses generating system

ABSTRACT

Briefly stated, the system in accordance with an object of the present invention, is related to a system for generating finite pulses from signals derived from a selected stage of a frequency divider receiving high frequency signals from a master oscillator, said pulses providing a drive control for an electric stepping motor of an electronic watch. The pulses generating system comprises two logical storage means, e.g two toggles in a master-slave arrangement, synchronised by sync. signals derived from a medium order divider stage and controlled by signals derived from lower order divider stage imposing the repetition frequency to said generated control pulses. The system embodiment, to which an operation control system means may be added, is realizable according to microelectronic integrated circuit techniques.

United States Patent 1 'Boudry Apr. 9, 1974 PULSES GENERATING SYSTEM Primary Examiner-Richard B. Wilkinson Assistant Examiner-U. Weldon [75] Inventor. Jean Marie Boudry, Paris, France Attorney, Agent or Firm cushman, Darby & [73] Assignee: Sescosem Societe Europeene de Semiconducteurs et de Cushman Microelectronique, Paris, France 221 Filed: June 28, 1972 [57] ABSTRACT Briefly stated, the system in accordance with an object [2]] Appl' 267056 of the present invention, is related to a system for generating finite pulses from signals derived from a se- [30] Foreign Application Priority Data lected stage of a frequency divider receiving high fre- July 9, l97l France 71.25179 q y Signals from a master Oscillator, Said Pulses providing a drive control for an electric stepping 52 1 us. Cl 58/723 R, 58/23 AC motor of an electronic watch- [Sl] Int. Cl G04c 1/00 Th pulses generating system comprises two logical l l Field Search 53/23 23 23 23 storage means, eg two toggles in a master-slave 58/23 23 4; 85, 696; 328/ 6, arrangement, synchronised by sync. signals derived 161 from a medium order divider stage and controlled by signals derived from lower order divider stage Reference-S Cited imposing the repetition frequency to said generated UNITED'STATES PATENTS control pulses. 3,363,410 1/ 1968 lmahashi 58/23 AC The system embodiment, to which an operation 3,416,057 12/1968 Froyd e al- 313/231 X control system means may be added, is realizable Hoffmann .i according to microelectronic integrated circuit techniques.

5 Claims, 5 Drawing Figures V MASTER OSClLLATOR n P N-l n m 2 1 Y" 5 I 9 I 1 L :1':- E il1l a r12 FREQUENCY DIVIDER F l 4 22 \J 1 -DECOD ER AND (R) POWER l SUPPLY l y l l I A L r- J t 1 TOGGLE TO 66 LE l .v I i B x i 1 1 T x B2 Y gtses- GENERATING SYSTEM 23 i I I L i PAIENIEUAPR 9 m4 1802.180 SHEET 2 (IF 4 I PATENTEDAPR 91914 3802190 I SHEET 3 BF 4 BL ZL I, v m

-HIIQ IJUL PATENTEDAPR 9 I974 I 3802.180 SHEET Mr 4 FREQUENCY DIVIDER PULSES" GENERATING SYSTEM CONTROL PULSES GENERATING SYSTEM The present invention relates to pulse generating systems provided for drive control of the electromechanical part of an electronic watch, the latter comprising in particular a master oscillator, an electronic frequency divider, a D.C. power supply, an electric stepping motor and a display system eg hands driven by said motor.

To this end, pulses of finite duration are required, for example in the order of milliseconds, which will control the drive of a stepping motor with a repetition frequency in the order of /2 Hz to 2 Hz. In addition, in the case of motors of the bipolar kind, two trains of control pulses M and M having the same duration and same repetition frequency, are required, the pulses in one train being time shifted with respect to those in the other by an interval equal to half a repetition rate. It is usual to refer to two such pulse trains as being interlaced.

It is well known to produce such pulse trains, M, and M by decoding, by a logical function means, signals picked up at carefully chosen points in the dividing stages of a frequency-divider to which is applied a signal from a master oscillator. However, this method has drawbacks such as:

- a large number of connection points have to be wired between the frequencydivider stages and the decoding circuits; 7

- it is necessary to have two separate decoder circuits in the case of bipolar motors which require two interlaced control pulse trains;

- substantial modifications to the decoder circuits and to the connections are necessary, in order to modify the characteristics of the control pulses.

The invention overcomes these drawbacks.

In the system in accordance with the invention, there are picked up at the outputs of predetermined stages of a frequency divider circuit:

l. synchronising signals H constituted by pulses whose duration is equal to the duration of the control pulses it is desired to produce;

2. recurrence signals R constituted by pulses whose duration is equal to halfthe repetition rate of the control pulses it is desired to produce.

These signals H and R are applied to predetermined inputs of a logic circuit arrangement comprising two synchronisable toggle circuits connected in a masterslave arrangement. The signals H are applied to the clock (or sync.) input of the first toggle circuit, whilst the complementary signals H are applied to. the clock input of the second toggle circuit. The signals R control the operation of the toggles and are applied to the control input of the first toggle.

The pulse trains M, and M, are obtained by decoding predetermined outputs of these two toggle circuits, the decoding being effected by a first and second logic gate, e.g. AND" gate, the first gate producing the pulses M, and the second the pulses M The invention will be better understood, and others of its features rendered apparent, from a consideration of the ensuing description and the attached drawings, in which:

FIG. I is a block diagram illustrating the principle of the invention;

FIG. 2 is one of the possible diagrams of the coupled toggle circuits constituting part of the invention;

FIGS. 3 and 4 are diagrams illustrating the functioning of the system;

FIG. 5 is a circuit diagram in accordance with the invention, including the addition of a system controlling the toggles operation and usable to modify the display system indication, for example for resetting the time.

In FIG. 1, part of the electronic circuitry of a watch has been illustrated, comprising:

- on the one hand, in the conventional manner, frequency divider stages numbered N, N-l, n, nl, 2, I, connected in series between the output 0 ofa master oscillator 10 providing a high frequency signal, e.g. 32 kHz, and a terminal S furnishing signals whose frequency has been reduced for example to l Hz.v

Each stage divides the frequency which it receives from the input of the preceding stage (or the oscillator in the case of stage N) by a constant factor, for example 2;

- On the other hand, in accordance with the invention, a pulse generating system for providing eontrol'pulses M, and M hereinbefore defined. This system comprises two synchronisable toggle circuits B, and B with two stable states, and two AND-gates 21 and 22.

The system arrangement is as follows:

The output of stage n of the frequency divider is connected to an input T of the toggle B, and, across an inverter 23 to a complemented input T of the toggle B This input T is complementary to that T. In other words, the toggle B changes state when its input signal is the complement of the input signal to toggle B,.

The output of a low-frequency divider stage, for example the stage 1, is connected to a control input I of the toggle 8,. The toggle B, has two complementary outputs X and X, and the toggle B has two complementary outputs Y and Y.

The inputs of the logic AND circuit 21, which produce at their output the pulses M,, are connected to the outputs X and T; the inputs of the logic AND circuit 22 producing th e pulses M at its output, are connected to the outputs X and Y.

Before explaining the operation of the system shown in FIG. '1, an embodiment of the circuits B, and B shown in FIG. 2 inside the broken line boxes, will be described in more detail. These toggle circuits comprise combinations of logic gates and inverters, the gates being opened or closed by the sync. signals, marked by H in FIGS. 1 and 2, coming from the output of a stage n. The AND gates 31 and 32 control the inputs to NAND-gates constituted by two AND-gates 33 and 34 whose outputs are taken to inverters 35 and 36. The assembly of circuits 33, 34, 35 and 36 constitutes a toggle circuit thanks to the loop connections effected between the output of the inverter 35 and an input of the NAND-gate 34, and between the output of the inverter 36 and an input of the NAND-gate 33. The same arrangements are encountered in toggle 8,, where the logic circuits 41 to 46 are similar to those of the circuits 31 and 36. The sync. signals H, via the terminal T, are supplied to the sync. inputs 311 and 321 of t he AND- gates 31 and 32. The complementary signals T are supplied to the corresponding inputs 411 and 421 of the AND-gates 41 and 42. Each toggle, which has two stable states, constitutes a store capa ble of holding a piece of binary data. The inputs T and T enable a new binary data value to be fed into each of the respective stores.

The repetition frequency signals R, coming from the output S at the lowest frequency of the divider shown in FIG. 1, arefed into the toggle B, through a control input J connected to an input 312 of the AND-gate 31,

and across an inverter 24 to an input 322 of the AND-.

sponse of the toggle circuits B, and B to the input pulses. The response of the toggles is illustrated in FIG.

3, for the general case in which the recurrent pulses R threshold V opening of. the AND-gates 31 and 32' by the action of the pulses H (at terminal T);

-threshold V,, closing of AND-gates 31 and '32, by

the pulses H;

- threshold V.,: opening of the AND-gates 41 and 42 by the pulses T.

The condition, which corresponds to a masterslave system operation, is a double one:

However, it is possible to realize gates of predetermined threshold, for example in the case where these gates are provided with diodes and resistors, by setting the respective resistances of each gate at a suitable value. If the set threshold condition is not complied with, then the transitions in the command signals must be sufficiently fast compared with the transit times of the signals through each toggle.

A full discussion of the potential states on the elements of the toggles B, and 8,, yields the results illustrated by the diagram of FIG. 3.

In this diagram, W, represents the high potential (I state) and W the low potential (0 state). At each point E, the potentials are plotted on the ordinates (EW axis) and the times on the abscissa (Et axis). The lines a, b, c, d, parallel to the axis EW, represent the characteristic instants at which the gates change state.

The interpretation of the diagram as far asthe potentials at the outputs X and Y are concerned, is as follows:

I. The pulse R at the terminal I is only transmitted to the output X at the instant b, that is to say after a delay at least equal to (b-a).

2. The pulse R is only transmitted. at the output Y at the instant d, that is to say after a delay at least equal to (d-a) 3. Consequently, the leading edges of the pulses X and Y are offset by a time period (d-b) which is in the order of magnitude of the duration of the sync. pulses H.

This is why the system of toggle circuits (which can take other forms than that described) is referred to as a D type toggle (D for delay).

FIG. 4 shows a diagram similar to that of FIG. 3, this time however covering the full period of the signals R. If D marks this period and I marks the duration of the pulses R, then using dividers which effect division by a factor of 2 and with rectangular signals, we have:

The response pulses of the synchronisable toggles have the same duration I and the same period D. However, the pulses X and Y are offset by an interval i which is substantially equal to half the period of the pulses H.

The decoding effected by the AND-gates 21 and 22 (FIG. I) in effect means the performance of the following logic functions:

It should be noted that to realize the decoding function it is possible to use logical circuits of the type AND, OR, NAND, NOR. In accordance of the type used, the output signals M, and M, are then inverted and/or changed-over.

In FIG. 4, the diagrams of the pulses M, and M, have beenshown. I

It will be seen:

I. that their durations are substantially equal to the duration i;

2. that their repetition rate D, is equal to D;

3. that their edges are offset by an interval equal to The examples described and illustrated are in no way [imitative of the scope of the invention. In particular, it is possible: 7

- to modify the duration i by deriving the sync. signals at the output of a different stage in the frequencydivider;

- to modify the period D by deriving the pulses R at a stage other than stage 1, and in certain cases the frequency-divider could be equipped with a supplementary frequency-divider stage connected at the output S of stage 1, in which case it would be at the output of this supplementary stage that the signal R would be picked up;

- to increase the number of toggle circuits B, and B in order to produce a pulse duration value I multiplied by 2, by 3, by 4, etc.

Another advantage of the invention resides in the possibility which it affords for adding a simple operation control system for resetting the time. By way of example, elements 51 to 57 have been illustrated in FIG. 5, which are intended to carry out this function. Two AND-gates 51 and 52 are connected in the manner indicated in FIG. 5, between the stages 1 and 3, an inverter being arranged between two respective inputs 512 and 522 of the AND-gates 51 and 52, the inputs 511 and 521 being connected to the respective outputs of the stages 3 and l. The input 512 is connected by a switch at terminal 56, either to a potential W, or to earth potential W The outputs of the AND-gates 51 and 52 are connected to the two inputs of an OR-gate 53 whose output is connected to an input of an AND- gate 54. To a second input of the AND-gate 54 either the potential W or earth potential W is applied by a switch 57, and the output of the AND-gate 54 is connected to the control input terminal J of the first toggle B Thanks to these complementary arrangements, it is possible to reset the time by modifying the operation of the toggles. The operation is broken into the following stages:

a. the motor is halted by inhibiting the AND-gate 54 (switch 57 set to earth potential W b. the motor is advanced at high speed by opening the AND-gate 51 (switch 56 to W,) an d the AND-gate 54 (switch 57 to W,);

e. the motor is advanced at normal speed by inhibiting the AND-gate 5] (switch 57 to potential W, and switch 56 to earth potential W In FIG. 5, a busbar 50 has been illustrated which makes it possible by a soldering operation, to switch the output of stages n+1, n, or n-l to the sync. signal input of toggle circuits B and B and thus modify the control pulses duration.

All the circuits described and illustrated hereinbefore are capable of integrated circuit design. Depending upon the electronic watch model involved, they differ from one another in terms of their electromechanical sections, it is possible to produce the different wiring arrangement simply by a minimal modification to the metallising mask and this is an additional advantage of the invention.

The invention is likewise applicable to an electronic watch which, either instead of the stepping motor or in addition to it, comprises a pulse counter which, by the emission of currents at predetermined intervals, actuates luminescent elements, for example electroluminescent diodes.

Of course, the invention is not limited to the embodiment described and shown which was given solely by way of example.

What is claimed, is:

l. A pulse generating system provided for the drive control of the electromagnetic part of an electric watch, said watch comprising a master oscillator, an electronic frequency divider connected to said oscillator-and including a plurality of dividing stages of higher order, of medium order, and lower order, an electric motor of the stepping operation type controlled by pulses having a finite duration and repetition frequency and a DC. power supply connected to said motor and wherein said pulse generating system comprises at least two logical system means for storing binary data, the first of said means comprising a control input terminal connected to the output of a frequency divider stage of said lower order for determining the repetition frequency of said pulses, a clock input terminal of said first means connected to an output of said medium order divider stage by a connecting means which allows the modification of the connection of one of said medium order stage for determining the duration of said pulse, said first means having at least two outputs, one of said first means outputs being a logical signal X output terminal and the other of said output terminals being a logical complementary signal X output terminal, and said second logical system means comprising at least first and sec ond control inputs connected respectively to X and X of said first means output terminals, a clock input terminal connected directly through an inverter means to said first means clock input terminal connection and said second means having two outputs, one logical signal Y output and one logical complementary signal Y; and wherein said pulse generating system in addition comprises decoding means including a logical arrangement comprising two AND gates having inputs connected to said logical outputs of said two logical system means, one of said gates receiving logical signals X and Y and ti e other of said gates receiving logical signals X and Y, the pulse generating system thereby providing two pulse trains of the same pulse duration and the same repetition frequency but offset in time, said decoding means being connected to said motor for coupling said two generated pulse trains thereto.

2. The system according to claim 1, wherein said two logical storing system means are bistable toggles of said D type or, in other words, a master-slave arrangement.

3. The system according to claim 1, wherein thesystem is in an integrated circuit embodiment.

4. The system according to claim 1, wherein said connecting means is a busbar connected by soldering means to an output terminal of said medium order divider stage and to said first and second clock inputs of the two logical system means.

5. The system according to claim 1, wherein the system comprises, connected to the control input terminal of said first logical system means, an operation control system comprising an AND gate for inhibiting control pulse transmission and actuated by switching means and an arrangement of a second AND gate connected to the upper stages of the lower frequency divider stages and a third AND gate connected to the lower stages of the low frequency divider stages, said both last mentioned gates being actuated by another switching means, said last mentioned gates being connected to the first gate by means of and OR gate thereby enabling modification of the repetition rate of said control pulses. 

1. A pulse generating system provided for the drive control of the electromagnetic part of an electric watch, said watch comprising a master oscillator, an electronic frequency divider connected to said oscillator and including a plurality of dividing stages of higher order, of medium order, and lower order, an electric motor of the stepping operation type controlled by pulses having a finite duration and repetition frequency and a D.C. power supply connected to said motor and wherein said pulse generating system comprises at least two logical system means for storing binary data, the first of said means comprising a control input terminal connected to the output of a frequency divider stage of said lower order for determining the repetition frequency of said pulses, a clock input terminal of said first means connected to an output of said medium order divider stage by a connecting means which allows the modification of the connection of one of said medium order stage for determining the duration of said pulse, said first means having at least two outputs, one of said first means outputs being a logical signal X output terminal and the other of said output terminals being a logical complementary signal X output terminal, and said second logical system means comprising at least first and second control inputs connected respectively to X and X of said first means output terminals, a clock input terminal connected directly through an inverter means to said first means clock input terminal connection and said second means having two outputs, one logical signal Y output and one logical complementary signal Y; and wherein said pulse generating system in addition comprises decoding means including a logical arrangement comprising two AND gates having inputs connected to said logical outputs of said two logical system means, one of said gates receiving logical signals X and Y and the other of said gates receiving logical signals X and Y, the pulse generating system thereby providing two pulse trains of the same pulse duration and the same repetition frequency but offset in time, said decoding means being connected to said motor for coupling said two generated pulse trains thereto.
 2. The system according to claim 1, wherein said two logical storing system means are bistable toggles of said ''''D'''' type or, in other words, a ''''master-slave'''' arrangement.
 3. The system according to claim 1, wherein the system is in an integrated circuit embodiment.
 4. The system according to claim 1, wherein said connecting means is a busbar connected by soldering means to an output terminal of said medium order divider stage and to said first and second clock inputs of the two logical system means.
 5. The system according to claim 1, wherein the system comprises, connected to the control input terminal of said first logical system means, an operation control system comprising an AND gate for inhibiting control pulse transmission and actuated by switching means and an arrangement of a second AND gate connected to the uPper stages of the lower frequency divider stages and a third AND gate connected to the lower stages of the low frequency divider stages, said both last mentioned gates being actuated by another switching means, said last mentioned gates being connected to the first gate by means of and OR gate thereby enabling modification of the repetition rate of said control pulses. 